1. Field of the Invention
This invention relates to flash electrically-erasable programmable read-only memories (flash EEPROM) and, more particularly, to methods for writing to such memories during intervals in which writing is prohibited in order to indicate the invalidity of data stored in such memories.
2. History of the Prior Art
Modern computer systems make extensive use of long term memory. Typically this memory is provided by one or more electro-mechanical hard (fixed) disk drives constructed of flat circular magnetic disks which rotate about a central axis and which have a mechanical arm to write to or to read from positions on the magnetic disk. Hard disk drives are very useful and have become almost a necessity to the operation of personal computers. However, such electro-mechanical drives are relatively heavy, require a significant amount of space within a computer, require a significant amount of the power in use, and are very susceptible to shock. A hard drive within a portable computer which is dropped is quite likely to cease functioning with a catastrophic loss of data.
Recently, forms of long term storage other than electro-mechanical hard disk drives have become feasible for use in computers. One of these is flash EEPROM. A flash EEPROM memory array includes a large plurality of floating-gate field effect transistors arranged as memory cells in typical row and column fashion with circuitry for accessing the individual cells and placing the memory transistors of those cells in one of two memory conditions. A flash memory cell, like a typical EPROM cell retains information when power is removed.
Flash EEPROM memory has a number of characteristics which adapt it to use as long term memory. It is light in weight, occupies very little space, and consumes less power than electro-mechanical disk drives. More importantly, it is especially rugged. It will withstand without adverse effects repeated drops each of which would destroy a typical electro-mechanical hard disk drive.
A difficulty with flash EEPROM, however, is that it is very slow to erase. Flash EEPROM is erased by applying a high voltage simultaneously to the source terminals of all of the transistors (cells) used in the memory. Because these source terminals are all connected to one another by metallic busing in the array, the entire array must be erased at once. While an electro-mechanical hard disk will typically store information in a first area of the disk and then rewrite that same area of the disk when the information changes, this is not possible with a flash memory array without erasing all of the valid information that remains in the array along with the invalid (dirty) information.
Because of this, a different arrangement is used for erasing dirty sectors of a flash EEPROM array. Such an arrangement is disclosed in detail in U.S. patent application Ser. No. 969,463, entitled Method and Circuitry for A Solid State Memory Disk, S. Wells, filed on even date herewith, and assigned to the assignee of the present invention. First, the entire array is divided into smaller separately erasable blocks so that when a block is erased the amount of valid data which must be reprogrammed is reduced. Typically, the array is composed of a number of silicon chips; and each such chip includes a number of such blocks. Then, when the information at a data entry changes, the changed information is written to a new sector on an available block rather than written over the old data; and the old data is marked dirty. When erasure occurs, all of the valid data in the block to be erased is written to a new block; and then the dirty block is erased and put back into use as a clean block of memory. Because of this involved erasure process, it typically takes as much as two seconds to erase a flash EEPROM array. However, because erasure need not occur with each entry which is rewritten, erasure may be delayed until a block contains a sufficient amount of dirty information that cleanup is feasible. This reduces the number of erasure operations to a minimum and allows erasure to occur in the background when the facilities for controlling the array are not otherwise occupied with reading and writing.
Because erasure takes so long, provision is made for suspending the erasure so that data may be read from a block in a silicon chip being erased. Write operations to the blocks of a chip of the array being erased are not allowed, however, because the circuitry which accomplishes the write operation is occupied with the erase process.
It is however, possible to write changed data to blocks on chips other than the chip containing the block being erased. The arrangement for writing simply finds unused space in the array and writes to that space. This is possible because the addressing scheme used treats the address as a logical address and records that logical address along with the physical address in a lookup table in random access memory associated with the control circuitry. The writing of data requires, however, that when updated data is rewritten to a new physical address, the lookup table entry be updated and the old entry in flash memory be marked as invalid (dirty). The old entry must be so marked because the RAM lookup table is destroyed when power is removed, and the entries in the flash EEPROM memory are reviewed to provide the data to reconstruct the lookup table each time power is applied. Normally, this causes no problem. However, if data being changed is stored in a block on a chip which is presently being erased, then the data cannot be marked as invalid during the erase process (even during a suspend) as this requires a write operation to a chip being erased. Consequently, the marking cannot be accomplished until the erase process has been completed.
If power is removed during this period, two entries will exist on power up without a method of distinguishing which is valid and which is invalid.